a. Field of Invention
This invention relates to apparatus and processes for automatically testing of electric circuits. More particularly, the invention relates to apparatus and processes for testing LSI components.
B. Description of the Prior Art
Data processing machines employ semiconductors to perform logical and memory operation at switching speeds of the order of 10 to 100 nanoseconds. Semiconductor components are fabricated in large scale integration (LSI) technologies. Several thousand circuits may be incorporated into a chip less than a quarter inch by a quarter inch in area. The circuits are combined to achieve the various machine functions. Each component must be tested for steady state or DC operation and dynamic or AC operation to verify that machine functions will be achieved. Testing of LSI components is becoming increasingly difficult because (1) switching states of the various active devices in the component change so fast (nanoseconds) that little or no stable or DC level is achieved to indicate whether a circuit is in a binary `1` or binary `0` condition and (2) the switching states of the active elements in the circuit change differently for identical circuits because of differences in distributed R, L, and C experienced by the circuit. A publication "Digest of Papers 1974 Semiconductor Test Symposium", of Nov. 5-7, 1974, sponsored by the IEEE Computer Society describes additional problems in dynamic time or AC testing of LSI components.
One method of testing is arranged so that the correct operation of the test system is not dependent on rise time, fall time or minimum delay of any individual circuit in a logic unit. The only dependency is that the total delay through a number of stages of logic is less than some known value. Such a test configuration is referred to as level sensitive scan logic as described in U.S. Pat. Nos. 3,761,695 or 3,783,254 or 3,784,907 all assigned to the present assignee. Briefly, the components under test include DC latch circuitry associated with the combinatorial and sequential logic networks. The latch circuitry is positioned along with the combinatorial logic networks and arranged in sets. The sets of latch circuitry are coupled through combinatorial logic to other sets of latches controlled by clock trains. All of the latches are coupled together to form a single shift register having a single input a single output in shift controls. Logic networks associated with different clocks can be isolated from a logic network under test. Test patterns are provided one at a time to the logic units under test. Each set of test patterns is shifted into the register and provided as input signals to the logic unit network. The contents of the shift register latches are measured at the unit outputs against the expected response of the particular test pattern thereby obtaining initial indication of the state of the storage circuits. Repeating this procedure with additional test patterns provides a clear indication of the test status of the individual logic networks and the component as a whole.
In another prior art test method, a circuit under test is connected in a close loop with input drive circuitry, delay and decoding circuitry. A test pattern is entered into the circuits as well as to the output of the apparatus. Isolations occur as a result of the closed loop connection. The isolations are measured by sequentially changing the binary signals applied to the apparatus and are an indication of the test status of the apparatus.
The prior art test methods either include circuit elements in a chip which take away from the potential logic performance or require complex test systems to determine the AC operation of the circuits. Both test systems are expensive and are limited in the degree to which they can test components.